The present invention relates generally to electronic packaging. More particularly, the present invention relates to a multi-component electronic package fabrication method.
As is well known to those of skill in the art, electronic devices such as cellular telephones employed a variety of electronic components. Typically, these electronic components included active chip components as well as passive chip components. An active chip component such as an integrated circuit was capable of performing an action such as execution of an instruction. In contrast, a passive chip component such as a resistor, capacitor, or inductor possessed a specific electrical characteristic yet was incapable of performing an action.
The passive chip components were not readily integratable into the active chip components. To illustrate, it was not economical to form all required resistors, capacitors, or inductors in an integrated circuit chip. For this reason, the active chip component was packaged into a package, hereinafter referred to as an IC package. The IC package and the passive chip components were then attached to the printed circuit mother board separate from one another.
As the art moved to smaller, lighter weight and less expensive electronic devices, passive chip components were combined with active chip components in a single package. FIG. 1 is a cross-sectional view of a multi-component package 10 in accordance with the prior art.
Referring now to FIG. 1, package 10 included a laminate substrate 12 having an upper surface 12U and a lower surface 12L. Formed on upper surface 12U were a plurality of traces 14 and a die attach metallization 16. Formed on corresponding traces 14 were contacts 18. An upper solder mask 20 covered upper surface 12U of substrate 12 and traces 14 yet left contacts 18 and die attach metallization 16 exposed.
A lower surface 22L of an active chip component 22, e.g., an integrated circuit, was attached to upper surface 12U, and, more particularly, to die attach metallization 16, by adhesive 24. Bond pads 26 on an upper surface 22U of active chip component 22 were electrically connected to corresponding contacts 18 by corresponding bond wires 28.
Terminals 30 of a passive chip component 32, e.g., a resistor, capacitor, or inductor, were electrically connected to corresponding contacts 18 by solder joints 34. In addition to forming the electrical connections between terminals 30 and the corresponding contacts 18, solder joints 34 also served to mount passive chip component 32 to substrate 12.
Active chip component 22 and passive chip component 32 were over molded in a layer of encapsulant 36. Layer of encapsulant 36 served to protect the electrical connections of package 10 as well as to protect package 10 from the ambient environment, e.g., moisture.
Traces 14 were electrically connected to corresponding traces 38 on lower surface 12L of substrate 12 by electrically conductive vias 40. Contacts 42 were formed on corresponding traces 38. A lower solder mask 44 covered lower surface 12L of substrate 12 and traces 38 yet left contacts 42 exposed.
Formed on contacts 42 were corresponding solder balls 46. As is well known to those of skill in the art, solder balls 46 were reflowed to attach and electrically connect package 10 to the printed circuit mother board. Solder joints 34 were formed of a solder having a higher melting temperature than that of solder balls 46 thus avoiding melting of solder joints 34 during reflow of solder balls 46. Solder balls 46 were arranged in an array format to form a ball grid array (BGA) package. Alternatively, a land grid array (LGA) or leadless chip carrier (LCC) package was formed.
By integrating passive chip component 32 with active chip component 22 into a single package 10, several advantages were realized as compared to attaching passive chip component 32 and active chip component 22 separately to the printed circuit mother board. One advantage was that less labor was required during component attachment to the printed circuit mother board. As a result, the cost of the electronic device employing package 10 was reduced. Another advantage was a reduction in final functional device size. However, when compared to a standard IC package containing only a single active chip component, package 10 was considerably larger, had reduced electrical performance and was significantly more expensive.
To minimize the cost associated with package 10, package 10 was often fabricated simultaneous with a plurality of packages 10 in an array format. FIG. 2 is a cross-sectional view of an array 50 of packages during fabrication in accordance with the prior art. Array 50 included a substrate 52. Substrate 52 included a plurality of individual substrates 12 integrally connected together. Substrate 52 was fabricated using well-known techniques.
Passive chip components 32 were then attached to each individual substrate 12. To illustrate, a first passive chip component 32A of the plurality of passive chip components 32 was attached to a first substrate 12A of the plurality of substrates 12.
To attach passive chip component 32A, solder paste was screened onto the appropriate contacts 18 on substrate 12A in a well-known manner. The solder paste included both solder and solder flux. Passive chip component 32A was positioned such that terminals 30 were aligned with and in contact with the screened solder paste. The screened solder paste was reflowed (melted) to mount passive chip component 32A to substrate 12A. The other passive chip components 32 were mounted to corresponding substrates 12 in a similar manner.
Since solder joints 34 were used to mount passive chip components 32 to corresponding substrates 12, a sufficient amount of solder paste had to be used to insure that solder joints 34 reliably mounted passive chip components 32. For the same reason, the solder flux of the solder paste was an aggressive, i.e., ionically active, solder flux.
Disadvantageously, the relatively large volume of solder paste contained a relatively large volume of aggressive solder flux. After mounting of passive chip components 32, a substantial amount of solder flux residue 52 from the solder flux remained. More particularly, solder flux residue 52 was left as a contaminant around solder joints 34 and on solder mask 20. Solder flux residue 52 was removed, e.g., using an aqueous cleaner.
FIG. 3 is a cross-sectional view-of array 50 at a further stage during fabrication. Referring now to FIG. 3, active chip components 22 were attached to each individual substrate 12 by adhesives 24. To illustrate, a first active chip component 22A of the plurality of active chip components 22 was attached to first substrate 12A by a first adhesive 24A of the plurality of adhesives 24.
Bond-pads 26 of active chip component 22A were then electrically connected to corresponding contacts 18 by corresponding bond wires 28. Bond pads 26 were wirebonded to contacts 18 by bond wires 28 sequentially. The other active chip components 22 were mounted and wirebonded in a similar manner. Typically, active chip components 22 were placed sequentially, adhesives 24 were cured, and bond pads 26 were sequentially wirebonded to contacts 18 by bond wires 28 for each active chip component 22.
FIG. 4 is a cross-sectional view of array 50 at a further stage during fabrication. Referring now to FIG. 4, a layer of encapsulant 56 was applied generally to cover an upper surface 52U of substrate 52. More particularly, layer of encapsulant 56 covered active chip components 22 including bond pads 26, bond wires 28, contacts 18, solder mask 20, passive chip components 32 including terminals 30 and solder joints 34. Illustratively, layer of encapsulant 56 was a liquid encapsulant formed using a liquid encapsulation process well known to those of skill in the art. Alternatively, layer of encapsulant 56 was a plastic encapsulant formed using a plastic encapsulation molded process also well known to those of skill in the art.
After formation and curing (if necessary) of layer of encapsulant 56, array 50 was singulated by cutting along singulation streets 60 resulting in a plurality of packages 10 (see FIG. 1, for example).
In accordance with the present invention, a package includes both a flip chip mounted active chip component and a passive chip component. By mounting the active chip component as a flip chip, several advantages are realized. One advantage is that the electrical performance of the package is improved compared to a conventional package having a wirebonded active chip component. More particularly, less impedance is associated with the flip chip bumps between the bond pads of the active chip component and the contacts on the substrate than that associated with conventional bond wires.
As the art moves towards higher speed active chip components, e.g., radio frequency (RF) integrated circuit components, it becomes increasingly important that the impedance associated with the package be minimized. Since the impedance of the package in accordance with the present invention is minimized, the package is well suited for use with higher speed active chip components.
Recall that in the prior art, a passive chip component was integrated with an active chip component into a single package. However, the incompatibility of the flip chip soldering process with the passive chip component soldering process required that the active chip component be wirebonded. Due to the relatively long length and relatively small diameter of a conventional bond wire, a relatively large impedance was associated with the bond wire. This relatively large impedance interfered with the propagation of the electrical signals to and from the active chip component. This interference was unacceptable depending on the application, e.g., in applications involving high frequency active chip components.
Further, by mounting the active chip component as a flip chip in accordance with the present invention, the area on the substrate occupied by the active chip component is reduced compared to the area occupied by a conventional wirebonded active chip component. More particularly, the contacts are formed within an area approximately equal to the area of the active chip component.
In contrast, to allow wire bonding, the contacts were fanned out around the perimeter of the active chip component in the prior art. Accordingly, the contacts necessarily occupied an area which was greater than the area of the active chip component.
Since the package in accordance with the present invention is formed to have a minimum size, the package is well suited for use with smaller, lighter weight and less expensive electronic devices.
Further, wirebonded active chip components of the prior art had an increased tendency to fail due to the so called xe2x80x9cpopcorn effectxe2x80x9d. As is well known to those of skill in the art, the die attach adhesive, which attached the active chip component to the substrate, had a tendency to absorb moisture. During attachment of the package to the print circuit mother board, this absorbed moisture had a tendency to expand due to heating. As a result, the active chip component was often damaged or destroyed resulting in failure of the package.
In stark contrast, the package in accordance with the present invention is formed without a die attach adhesive. Accordingly, the popcorn effect associated with conventional die attach adhesives is eliminated. As a result, the reliability of the package is greater than that of a package of the prior art.
To minimize the cost of the package, in one embodiment, the package is formed simultaneously with a plurality of packages. Solder joints are formed to mount passive chip components to an array type substrate, the array type substrate including a plurality of individual substrates integrally connected together. Since the solder joints form the physical mounting for the passive chip components, a substantial amount of solder paste is used resulting in the generation of a substantial amount of solder flux residue. After formation of the solder joints, the solder flux residue is removed.
Flip chip bumps form the electrical interconnections between the bond pads of the active chip components and the contacts on the array type substrate. However, since the flip chip bumps have minimal volume and are not primarily responsible for mounting the active chip components to the array type substrate, the flip chip bumps are formed using only a minimal amount of solder flux. Accordingly, the flip chip bumps are formed generating only a minimal amount of solder flux residue.
In one embodiment, the flip chip bumps are formed of a solder having a lower melting temperature than the solder of the solder joints. In this manner, the flip chip bumps are selectively melted and reflowed.
Thus, in accordance with the present invention, two previously incompatible soldering processes have been integrated into a single process. More particularly, the passive chip components are first soldered to the substrates using a residue generating soldering process followed by soldering of the active chip components using a minimal residue generating soldering process.
In one particular embodiment, a substrate has an upper surface having a first trace and a second trace formed thereon. A passive chip component has a first terminal and a solder joint electrically connects the first terminal to the first trace. An active chip component has a first surface with a bond pad formed thereon and a flip chip bump electrically connects the bond pad to the second trace.
In another embodiment, a substrate has an upper surface having a passive chip component trace and an active chip component trace formed thereon. A passive chip component has a surface with a first terminal formed thereon. A first contact is on the passive chip component trace and a solder joint electrically connects the first terminal to the first contact. An active chip component has a first surface with a bond pad formed thereon. A second contact is on the active chip component trace and a flip chip bump electrically connects the bond pad to the second contact such that the active chip component is mounted as a flip chip.
Also in accordance with the present invention, a method includes screening a solder paste onto a first contact on a first surface of a substrate. The solder paste includes a first solder and a first solder flux. A terminal of a passive chip component is aligned with the solder paste. The solder paste is melted to form a solder joint between the first contact and the terminal. Solder flux residue from the first solder flux is removed. A solder bump is formed on a bond pad on a first surface of an active chip component. The solder bump is aligned with a second contact on the first surface of the substrate. The solder bump is melted to form a flip chip bump between the second contact and the bond pad, where the solder joint does not melt during the melting of the solder bump.
In another embodiment, a method includes mounting a passive chip component to a substrate. A bond pad of an active chip component is aligned with a contact on the substrate. The active chip component is mounted as a flip chip on the substrate by forming a flip chip bump between the bond pad and the contact.
These and other features and advantages of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.